It adds 3 and subtracts 1 instead of adding just 1

All above speculations are basically missing the problem.

the design is working fully correct!

Ít only looks like an error. The problem is that internal nodes are not guaranteed to be shown correct (e. g. without inverting bits) by the Quartus simulator (in timing simulation). They are shown as the design uses them after optimisation. If you add an output port, that simply copies the state of the nombre signal,you'll see immediately that the design is counting correct, but showing some inverted bits. The reason is very simple, the reset state of "0101010101" is mapped to "00000000", all registers are reset to zero, in other word an XOR with "0101010101" gets the correct result. You have to consult the Technology Map instead of RTL Viewer to see this behaviour.