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Altera_Forum
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17 years ago

It adds 3 and subtracts 1 instead of adding just 1

Hi! I'm pretty new with vhdl and Quartus II and maybe this question is too obvious, but I spent three days on it and I cannot understand yet why is not working... I made a silly program, just addi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

First of all thanks you for all your answers. I've understood a lot of things with your posts.

I consulted The Technology Map and this behaviour can be seen, all clr are connected to the reset, so the reset is done by "00000" instead of "10101". So the values (of internal signal) I obtained in the simulation are correct if I make a XOR with "10101". Moreover I create another output as you suggested me and I can see the correct values of the counting. Now I know that my design is correct, but I don't understand why it does that. If my design is more complicated how can I see the correct values of internal signals? Only routing them as an output? How mapping is made? Can I set anything to "force" the mapping?

I searched on the Quartus Handbook but i couldn't found any information about maping. Could anyone recommend me anything to read? I searched also in Internet but i couldn't found anything.

thanks again