It adds 3 and subtracts 1 instead of adding just 1

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It's VHDL not C!

Variable command should never exist..

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You're right in so far, that there isn't a reason to use a variable here. But apart from that, variables are existing as objects in VHDL specification, and they have a purpose. Some VHDL constructs must use variables, others may use it to achieve specific behaviour (Variable assignments behave similar to blocking assignments in Verilog). And in many places, a confused VHDL programmer could use it without causing a different behaviour than when using signals. But it's bad programming style.