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Altera_Forum's avatar
Altera_Forum
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9 years ago

inout wire logic, quartus15.1, error

Using Quartus 15.1 I have the following issue,

when I'm using this construction

- inout wire logic [31:0] SIG1; - it is working correctly,

but when I define logic [31:0] in typedef into package and using import package, how

- package def_type;

typedef logic [31:0] SIG1_WIDTH_T;

endpackage

inout SIG1_WIDTH_T SIG1;

The Quartus send me an Error (10170): Verilog HDL syntax error..

The last one scheme is run correctly by Synplify & NCSIM, and Quartus 15.1 according it's Help supports Package & User-defined types

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Hello,

    It's true that Quartus 15.1 supports package and user-defined types. Could you share your entire code? ( File which contains package and another file which contains your port declaration.) Also please post full message for your error.

    Thanks,

    Bhaumik
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    Hello,

    It's true that Quartus 15.1 supports package and user-defined types. Could you share your entire code? ( File which contains package and another file which contains your port declaration.) Also please post full message for your error.

    Thanks,

    Bhaumik

    --- Quote End ---

    It's full code, which ended with error:

    Error (10170): Verilog HDL syntax error at tst_package.sv(8) near text: "SIG1"; expecting ")". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. 

    package state_type; 
    typedef logic  SIG1_WIDTH_T;
endpackage
import state_type::*;  // import package definitions into $unit
module tst_sv(
    inout wire SIG1_WIDTH_T SIG1//not working
    //inout wire logic  SIG1//working correctly
);
endmodule
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Hi,

    You are using 'wire' and 'logic' both types. According to me only single type should be used.

    Try following :

    package state_type;

    typedef wire [31:0] SIG1_WIDTH_T;

    endpackage

    import state_type::*; // import package definitions into $unit

    module tst_sv(

    inout SIG1_WIDTH_T SIG1//not working

    //inout wire logic [31:0] SIG1//working correctly

    );

    endmodule

    It should work.

    Thank you,

    Bhaumik
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    `wire logic` is legal SystemVerilog. wire is the signal kind, and logic is the data type. The other kind of signal is var for variable. This syntax was added in 1800-2009. To be backward compatible with Verilog, logic is the implicit data type for a wire. SystemVerilog allows other data types like structs and enums on wires. Quartus may not support this yet.

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Let's view below code, while inout wire logic defines directly it works correctly, but when I try to use logic whithout wire - I get error from Quartus -

    Error (10663): Verilog HDL Port Connection error at tst_package.sv(35): output or inout port "SIG1" must be connected to a structural net expression 

    
package state_type; 
    typedef logic  SIG1_WIDTH_T;
endpackage
import state_type::*;  // import package definitions into $unit
module inner_m(
    input EN,
    input SIG1_WIDTH_T IN1,
    output SIG1_WIDTH_T OUT1,
    inout SIG1_WIDTH_T SIG1//not working
    //inout wire logic  SIG1//working correctly
);
assign SIG1 = EN ? IN1 : 'z;
assign OUT1 = SIG1;
endmodule
module tst_sv(
    input EN,
    input SIG1_WIDTH_T IN1,
    output SIG1_WIDTH_T OUT1,
    inout SIG1_WIDTH_T SIG1//not working
    //inout wire logic  SIG1//working correctly
);
inner_m inner_m(
    .EN    (EN),
    .IN1    (IN1),
    .OUT1    (OUT1),
    .SIG1    (SIG1)
);
endmodule
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    inout wire SIG1_WIDTH_T SIG1

    - Yes, I have try it, and get error -

    Error (10170): Verilog HDL syntax error at tst_package.sv(11) near text: "SIG1"; expecting ")". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    --- Quote Start ---

    `wire logic` is legal SystemVerilog. wire is the signal kind, and logic is the data type. The other kind of signal is var for variable. This syntax was added in 1800-2009. To be backward compatible with Verilog, logic is the implicit data type for a wire. SystemVerilog allows other data types like structs and enums on wires.

    --- Quote End ---

    Thank you. I was not aware about this.

    Cheers,

    Bhaumik
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    This seems like a support issue for Quartus.

    --- Quote End ---

    I think so, but I don't know any way to connect with support altera. I only rely that they are reading this forum