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Altera_Forum
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9 years ago

inout wire logic, quartus15.1, error

Using Quartus 15.1 I have the following issue, when I'm using this construction - inout wire logic [31:0] SIG1; - it is working correctly, but when I define logic [31:0] in typedef into ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Let's view below code, while inout wire logic defines directly it works correctly, but when I try to use logic whithout wire - I get error from Quartus -

Error (10663): Verilog HDL Port Connection error at tst_package.sv(35): output or inout port "SIG1" must be connected to a structural net expression 


package state_type; 
    typedef logic  SIG1_WIDTH_T;
endpackage
import state_type::*;  // import package definitions into $unit
module inner_m(
    input EN,
    input SIG1_WIDTH_T IN1,
    output SIG1_WIDTH_T OUT1,
    inout SIG1_WIDTH_T SIG1//not working
    //inout wire logic  SIG1//working correctly
);
assign SIG1 = EN ? IN1 : 'z;
assign OUT1 = SIG1;
endmodule
module tst_sv(
    input EN,
    input SIG1_WIDTH_T IN1,
    output SIG1_WIDTH_T OUT1,
    inout SIG1_WIDTH_T SIG1//not working
    //inout wire logic  SIG1//working correctly
);
inner_m inner_m(
    .EN    (EN),
    .IN1    (IN1),
    .OUT1    (OUT1),
    .SIG1    (SIG1)
);
endmodule