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Altera_Forum
Honored Contributor
Honored Contributorinout wire logic, quartus15.1, error
Using Quartus 15.1 I have the following issue, when I'm using this construction - inout wire logic [31:0] SIG1; - it is working correctly, but when I define logic [31:0] in typedef into ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- This seems like a support issue for Quartus. --- Quote End --- I think so, but I don't know any way to connect with support altera. I only rely that they are reading this forum
