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Altera_Forum
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9 years ago

inout wire logic, quartus15.1, error

Using Quartus 15.1 I have the following issue, when I'm using this construction - inout wire logic [31:0] SIG1; - it is working correctly, but when I define logic [31:0] in typedef into ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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`wire logic` is legal SystemVerilog. wire is the signal kind, and logic is the data type. The other kind of signal is var for variable. This syntax was added in 1800-2009. To be backward compatible with Verilog, logic is the implicit data type for a wire. SystemVerilog allows other data types like structs and enums on wires.

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Thank you. I was not aware about this.

Cheers,

Bhaumik