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Altera_Forum
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9 years ago

inout wire logic, quartus15.1, error

Using Quartus 15.1 I have the following issue, when I'm using this construction - inout wire logic [31:0] SIG1; - it is working correctly, but when I define logic [31:0] in typedef into ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Hello,

It's true that Quartus 15.1 supports package and user-defined types. Could you share your entire code? ( File which contains package and another file which contains your port declaration.) Also please post full message for your error.

Thanks,

Bhaumik

--- Quote End ---

It's full code, which ended with error:

Error (10170): Verilog HDL syntax error at tst_package.sv(8) near text: "SIG1"; expecting ")". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. 

package state_type; 
    typedef logic  SIG1_WIDTH_T;
endpackage
import state_type::*;  // import package definitions into $unit
module tst_sv(
    inout wire SIG1_WIDTH_T SIG1//not working
    //inout wire logic  SIG1//working correctly
);
endmodule