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Altera_Forum's avatar
Altera_Forum
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9 years ago

inout wire logic, quartus15.1, error

Using Quartus 15.1 I have the following issue, when I'm using this construction - inout wire logic [31:0] SIG1; - it is working correctly, but when I define logic [31:0] in typedef into ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi,

You are using 'wire' and 'logic' both types. According to me only single type should be used.

Try following :

package state_type;

typedef wire [31:0] SIG1_WIDTH_T;

endpackage

import state_type::*; // import package definitions into $unit

module tst_sv(

inout SIG1_WIDTH_T SIG1//not working

//inout wire logic [31:0] SIG1//working correctly

);

endmodule

It should work.

Thank you,

Bhaumik