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Altera_Forum
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9 years ago

inout wire logic, quartus15.1, error

Using Quartus 15.1 I have the following issue, when I'm using this construction - inout wire logic [31:0] SIG1; - it is working correctly, but when I define logic [31:0] in typedef into ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

inout wire SIG1_WIDTH_T SIG1

- Yes, I have try it, and get error -

Error (10170): Verilog HDL syntax error at tst_package.sv(11) near text: "SIG1"; expecting ")". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.