Altera_Forum
Honored Contributor
11 years agoHow to use ip-generate on a hierarchical sys system
Hi,
I am using ip-generate to compile a Qsys design into Verilog code than can be programmed into the FPGA and test benches for simulation. I have a single level Qsys system working, but my primary target has several qsys subsystems within a top level Qsys system. Can I use ip-generate directly to compile the hierarchical Qsys system? Do you have any example scripts which show how to do that? My current script reports the underlying sys sub-systems are "not found" even if I actually copy them to the local dir. If the hierarchical project cannot be compiled in one go with ip-generate as can be done by the GUI. What is the recommended multi-step process and what are the recommended intermediate targets for a Makefile? Thanks Martin ps. I don’t see arguments to direct ip-generate to create a test bench but I did see an example which seemed to use a testbench specific .qsys file. !? What’s the best way to use ip-generate to creat a testbecnh from a .qsys system?