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Altera_Forum's avatar
Altera_Forum
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11 years ago

How to use ip-generate on a hierarchical sys system

Hi, I am using ip-generate to compile a Qsys design into Verilog code than can be programmed into the FPGA and test benches for simulation. I have a single level Qsys system working, but my pri...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I don't know the answer to the hierarchy question, but I have a suggestion that might work ...

To determine what arguments to pass to ip-generate, I use the GUI and then copy the ip-generate arguments into a script, eg., this BeMicroCV design has an example for the DDR controller (see the zip file with post#5)

http://www.alteraforum.com/forum/showthread.php?t=43992

If you use "generate" from the Qsys GUI, the logging dialog box most likely has the sequence you need.

The same thing goes for generating simulation files; check the checkboxes in the GUI, click generate, and look at the log in the dialog that pops up.

Cheers,

Dave