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Altera_Forum's avatar
Altera_Forum
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11 years ago

How to use ip-generate on a hierarchical sys system

Hi, I am using ip-generate to compile a Qsys design into Verilog code than can be programmed into the FPGA and test benches for simulation. I have a single level Qsys system working, but my pri...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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I can do it in the GUI.

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Can you copy-and-paste the contents of the generate GUI and email it to me (to my forum name), or just post it to this thread as a .txt attachment. It'll help to see the complete output.

I'm not sure that I'll be able to find a solution, but at least I can confirm its confusing, and you could then file a Service Request with Altera :)

Lets see if we can figure it out first ...

Cheers,

Dave