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Altera_Forum
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11 years ago

How to use ip-generate on a hierarchical sys system

Hi, I am using ip-generate to compile a Qsys design into Verilog code than can be programmed into the FPGA and test benches for simulation. I have a single level Qsys system working, but my pri...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hey Martin,

Since you are playing with these tools, take a look at de0_nano_sdram.zip in this thread;

http://www.alteraforum.com/forum/showthread.php?t=45927

The thing you want to look at is scripts/qsys_system.tcl, i.e., the Qsys system has been converted to a Tcl script, rather than an XML file. This allows the differences in Quartus versions to be absorbed into the Tcl. For example, the SDRAM controller parameters have changed.

I suspect that your hierarchical qsys system could be converted to several Tcl scripts that might be a little easier to maintain ...

Cheers,

Dave