Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

How to use ip-generate on a hierarchical sys system

Hi, I am using ip-generate to compile a Qsys design into Verilog code than can be programmed into the FPGA and test benches for simulation. I have a single level Qsys system working, but my pri...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

That was a great suggestion Dave.

I have progressed further, but I am having trouble figuring out the steps to generate the SoC BFM based simulation test benches.

I can do it in the GUI.

It is one click on "Generate HDL test benches"

In the log file I see 2 x calls to ip-generate but there is a call to a TC script tbgen.tcl in between

Only the output of that script is shown in the report file so I cannot see how it is called.

There is a comment in the script file

/tools/altera/14.0/./quartus/sopc_builder/bin/tbgen.tcl

which suggest it may be called by sop_builder, but I cannot find a command line exec for sop_builder.

Any suggestions on tracking down the exact calls made by the GUI?

Thanks again Martin