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Altera_Forum
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11 years ago

How to use ip-generate on a hierarchical sys system

Hi, I am using ip-generate to compile a Qsys design into Verilog code than can be programmed into the FPGA and test benches for simulation. I have a single level Qsys system working, but my pri...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

ps. a find returns:

/tools/altera/./14.0/quartus/sopc_builder

/tools/altera/./14.0/quartus/sopc_builder/bin/sopc_builder.jar

/tools/altera/./14.0/quartus/sopc_builder/bin/sopc_builder.ptf

/tools/altera/./14.0/quartus/sopc_builder/model/bin/sopc_builder.pl

/tools/altera/./14.0/ip/altera/ddr_high_perf/lib/sopc_builder

/tools/altera/./14.0/ip/altera/ddr_ddr2_sdram/lib/sopc_builder

/tools/altera/./14.0/ip/altera/ddr3_high_perf/lib/sopc_builder

/tools/altera/./14.0/ip/altera/pci_compiler/lib/sopc_builder

/tools/altera/./14.0/ip/altera/pci_compiler/sopc_flow/example/sopc_builder_example_readme.txt

/tools/altera/./14.0/ip/altera/sopc_builder_ip

/tools/altera/./14.0/ip/altera/ddr2_high_perf/lib/sopc_builder

/tools/altera/./14.0/qprogrammer/sopc_builder