FSM: a state gets latched

Seems pretty obvious that reset is being asserted somehow. I would focus on that. And don't just look at the external reset signal. Feed the internal rst_L_sys signal out to a test point and look at it.

Is it possible that the FPGA configuration is being cleared, possibly due to a POR reset? Depending upon how your LEDs are being driven you may not be able to tell the difference between the SM sitting in the INIT state vs. the FPGA not configured.

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Seems pretty obvious that reset is being asserted somehow. I would focus on that. And don't just look at the external reset signal. Feed the internal rst_L_sys signal out to a test point and look at it.

Is it possible that the FPGA configuration is being cleared, possibly due to a POR reset? Depending upon how your LEDs are being driven you may not be able to tell the difference between the SM sitting in the INIT state vs. the FPGA not configured.

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Its not an external reset, which is suppose to come from my microcontroller, , i made sure of that.

I dont think its a POR bacause i am outputting another led, a test led that is blinking at the rate of the arbiter that you can find in the file i uploaded, the first always block...

So the FPGA is "alive" and keeps working, but the state machine, for whatever reason, is being thrown to INIT, and latches there.

So when your state machine transitions to the INIT state when you get stuck, what is the immediate prior sequence of state(s). IE, where does it come from?

Your INIT state is encoded as state '0', so if your code loads the state register, or clears the state register, you will get to state INIT.

Do you have a simulation test bench that you are using to validate your design prior to loading into the FPGA? If you don't, you should. Write one right now.

I NEVER load a design into hardware without validating it first in a testbench. You can spend hours and hours debugging in hardware what is obvious from a testbench failure.

I do have a testbanch and i did run a simulation.

Didn't see this behavior... Though i didn't spend a lot of time to simulate every possible situation..

My system is driven by en external trigger.

At the moment i still havent found a specific sequence that leads to the latch, though i know 3 things for sure:

1. The system can stay forever at WAIT state. No problem there.

2. The system can work great for a couple of sequence and then gets stuck, or gets stuck imidiatly at the first trigger.

3. When in INIT state, the FPGA keeps working, beside the state machine...

Really strange...

I am open to any sugestion, really anything

Did you monitor all state variable bits, e.g. with SignalTap? Do you see exactly INIT state, or an illegal combination of state variable bits in stucked state?

Assuming the FSM is synthesized using the default one state hot style, there's basically a possibility to get stuck in an unrecoverable illegal state, particularly if the input signals like TRIG violate timing requirements.

You may try to enforce safe state machine encoding by a synthesis attribute (review Quartus software manual how to apply it). To avoid timing violations of FSM input signals, use synchronizers.

The external trigger is asynchronous but i use an edge detector to start the FSM, so as far as the FSM's concern, the trigger is synchronized.

I see a latch on a full state, INIT state and not some unrecignized state.

But maybe the synthesizer is changing my binary style i will try to look into that.

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so as far as the FSM's concern, the trigger is synchronized.

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No, the positive transition of TRIG[0] is directly evaluated by the state machine logic without previous synchronization. trig_risedge_SI is generated in combinational logic. If the transition coincides with the active clock edge, delay skew can cause an inconsistent state variable result.

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But maybe the synthesizer is changing my binary style i will try to look into that.

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It surely does, unless you specify an encoding by synthesis attributes. Review Quartus software manual about FSM coding styles.

I can't say if the sketched problem is actually causing the observed FSM failure. But it surely can and is a "popular" fault when designing synchronous logic processing asynchronous input signals.

Sorry, i am not sure i fully understand why the FSM "see" an asynchronous signal and if so how can i fix it.I also cant comprehend what series of events can cause an undesired state...

I would gladly recieve any feedback from you, so i can improve my understanding and my design.

As i see it, the FSM is driven only by a rising edge detection, which is sampled by the clock wich serves the FSM module...

The first always block is not related to the FSM itself and could be easilly be placed outside the module.

You can tell Quartus to build safe state machines. Go into Assignments -> Settings -> Compiler Settings -> Advanced Settings (Synthesis) and set "Safe State Machine" to On. This should prevent the state machine from staying stuck in an illegal state. This could be a useful experiment but obviously you need to understand why you're getting into the illegal state to begin with.

Good luck.

Ok, so a quick update, i changed synthesis preferences to not interfere with my FSM, things look better.

I still need to understand why things went wrong...