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Seems pretty obvious that reset is being asserted somehow. I would focus on that. And don't just look at the external reset signal. Feed the internal rst_L_sys signal out to a test point and look at it.
Is it possible that the FPGA configuration is being cleared, possibly due to a POR reset? Depending upon how your LEDs are being driven you may not be able to tell the difference between the SM sitting in the INIT state vs. the FPGA not configured.
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Its not an external reset, which is suppose to come from my microcontroller, , i made sure of that.
I dont think its a POR bacause i am outputting another led, a test led that is blinking at the rate of the arbiter that you can find in the file i uploaded, the first always block...
So the FPGA is "alive" and keeps working, but the state machine, for whatever reason, is being thrown to INIT, and latches there.
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