FSM: a state gets latched

I do have a testbanch and i did run a simulation.

Didn't see this behavior... Though i didn't spend a lot of time to simulate every possible situation..

My system is driven by en external trigger.

At the moment i still havent found a specific sequence that leads to the latch, though i know 3 things for sure:

1. The system can stay forever at WAIT state. No problem there.

2. The system can work great for a couple of sequence and then gets stuck, or gets stuck imidiatly at the first trigger.

3. When in INIT state, the FPGA keeps working, beside the state machine...

Really strange...

I am open to any sugestion, really anything