FSM: a state gets latched

Did you monitor all state variable bits, e.g. with SignalTap? Do you see exactly INIT state, or an illegal combination of state variable bits in stucked state?

Assuming the FSM is synthesized using the default one state hot style, there's basically a possibility to get stuck in an unrecoverable illegal state, particularly if the input signals like TRIG violate timing requirements.

You may try to enforce safe state machine encoding by a synthesis attribute (review Quartus software manual how to apply it). To avoid timing violations of FSM input signals, use synchronizers.