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Honored Contributor
Honored ContributorFSM: a state gets latched
Hi, i am running a state machine. Simulation shows everything is OK. Real life implementation is showing otherwise. I keep track of the states using on board LEDS showing the current FSM st...
Altera_ForumHonored Contributor
Honored ContributorSorry, i am not sure i fully understand why the FSM "see" an asynchronous signal and if so how can i fix it.I also cant comprehend what series of events can cause an undesired state...
I would gladly recieve any feedback from you, so i can improve my understanding and my design. As i see it, the FSM is driven only by a rising edge detection, which is sampled by the clock wich serves the FSM module... The first always block is not related to the FSM itself and could be easilly be placed outside the module.
