FSM: a state gets latched

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so as far as the FSM's concern, the trigger is synchronized.

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No, the positive transition of TRIG[0] is directly evaluated by the state machine logic without previous synchronization. trig_risedge_SI is generated in combinational logic. If the transition coincides with the active clock edge, delay skew can cause an inconsistent state variable result.

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But maybe the synthesizer is changing my binary style i will try to look into that.

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It surely does, unless you specify an encoding by synthesis attributes. Review Quartus software manual about FSM coding styles.

I can't say if the sketched problem is actually causing the observed FSM failure. But it surely can and is a "popular" fault when designing synchronous logic processing asynchronous input signals.