FSM: a state gets latched

So when your state machine transitions to the INIT state when you get stuck, what is the immediate prior sequence of state(s). IE, where does it come from?

Your INIT state is encoded as state '0', so if your code loads the state register, or clears the state register, you will get to state INIT.

Do you have a simulation test bench that you are using to validate your design prior to loading into the FPGA? If you don't, you should. Write one right now.

I NEVER load a design into hardware without validating it first in a testbench. You can spend hours and hours debugging in hardware what is obvious from a testbench failure.