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Honored Contributor
Honored ContributorFSM: a state gets latched
Hi, i am running a state machine. Simulation shows everything is OK. Real life implementation is showing otherwise. I keep track of the states using on board LEDS showing the current FSM st...
Altera_ForumHonored Contributor
Honored ContributorSeems pretty obvious that reset is being asserted somehow. I would focus on that. And don't just look at the external reset signal. Feed the internal rst_L_sys signal out to a test point and look at it.
Is it possible that the FPGA configuration is being cleared, possibly due to a POR reset? Depending upon how your LEDs are being driven you may not be able to tell the difference between the SM sitting in the INIT state vs. the FPGA not configured.
