Forum Discussion
Honored ContributorFlattening Verilog Hierarchy for IP block creation
Guys,
Wonder if someone could point me in the right direction. I would like to flatten my design hierarchy into 1 file so I can just encrypt that one file for making an IP block. With over 60 files (and include files) a manual process of creating one file is taking ages. I know that quartus has the VQM writer in but design support was removed for cyclone 3 onwards (I am using a cyclone 3). I am aware of .qxp file and have used it in the past but I don't think it can be encrypted. Anyone know of anything within Quartus or anything else I would really appreciate a point in the right direction. Best Regards C13 Replies
Altera_Forumwrite a script to dump all of the modules in to one file. at that point you might as well have written a script that individually encrypts each source file
- Altera_Forum
How are you encrypting them? Using Altera's tools for encryption and licensing? I've never done it before(actually, I did about ten years ago, but assume things have changed), but have never heard of anyone saying they needed to combine them all. Are you sure that step is necessary?
- Altera_Forum
I've used Altera's AMPcrypt tool for that. you only have to encrypt your top level entity, and then create the .qxp file.
you'll need to contact Altera directly to get that tool. By the way I think I've heard that the new Verilog \ VHDL versions include a built in encryption attribute, but I haven't tried it myself, and I don't know how much Quartus support there is. - Altera_Forum
Thanks for your replies.
Rysc, Yes I am using Ampcrypt. You are correct that there is no need to combine the packages. However, as the design is over 60 files I would rather combine them for an easier IP delivery. The brick, So are you saying I could encrypt the design and then export a .qxp? I don't want to just encrypt my top level as there is nothing really in there. Great replies, Thanks for your continued support C - Altera_Forum
So I tried what 'The brick said'. Looks like you can encrypt your source files and then export the encrypted file as a .qxp and then use the .qxp as normal.
Not tried it in silicon yet but I'll give it a go. C - Altera_Forum
I have done and it works. to test that it is actually encrypted, I compiled a "wrapper design" with normal and encrypted qxp.
with the normal design I could make ECO changes in the technology map viewer, but with the encrypted qxp I couldn't. If I remember correctly, you can see some of the hierarchy building blocks (but not the inside logic). - Altera_Forum
The brick,
Great Thanks for your help. For some reason I though that would not work :confused: Anyway I think that's me sorted. Thanks for your help (and to the others for replying) C - Altera_Forum
it's generally considered a workaround to use .qxp files for IP distribution. if you have the ampcrypt tool i wouldn't use .qxp
- Altera_Forum
The Pancake,please explain how do you distribute your IP?
- Altera_Forum
clear text
keep in mind the core is no longer parameterizable or portable across families if you distribute with .qxp i would distribute the entire core as ampcrypt encrypted HDL (1 file with many modules or individual files with 1 module each - it's just a matter of preference) and provide simgen instructions/scripts for the user to generate a simulation model like Altera's IP actually, the best solution might be one of the encryption methods that's readable by both Quartus and simulators (like the Stratix V models)
