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Altera_Forum's avatar
Altera_Forum
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14 years ago

Flattening Verilog Hierarchy for IP block creation

Guys, Wonder if someone could point me in the right direction. I would like to flatten my design hierarchy into 1 file so I can just encrypt that one file for making an IP block. With ove...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I have done and it works. to test that it is actually encrypted, I compiled a "wrapper design" with normal and encrypted qxp.

with the normal design I could make ECO changes in the technology map viewer, but with the encrypted qxp I couldn't.

If I remember correctly, you can see some of the hierarchy building blocks (but not the inside logic).