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Altera_Forum
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14 years ago

Flattening Verilog Hierarchy for IP block creation

Guys, Wonder if someone could point me in the right direction. I would like to flatten my design hierarchy into 1 file so I can just encrypt that one file for making an IP block. With ove...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

How are you encrypting them? Using Altera's tools for encryption and licensing? I've never done it before(actually, I did about ten years ago, but assume things have changed), but have never heard of anyone saying they needed to combine them all. Are you sure that step is necessary?