Flattening Verilog Hierarchy for IP block creation

clear text

keep in mind the core is no longer parameterizable or portable across families if you distribute with .qxp

i would distribute the entire core as ampcrypt encrypted HDL (1 file with many modules or individual files with 1 module each - it's just a matter of preference) and provide simgen instructions/scripts for the user to generate a simulation model like Altera's IP

actually, the best solution might be one of the encryption methods that's readable by both Quartus and simulators (like the Stratix V models)