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Altera_Forum's avatar
Altera_Forum
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14 years ago

Flattening Verilog Hierarchy for IP block creation

Guys, Wonder if someone could point me in the right direction. I would like to flatten my design hierarchy into 1 file so I can just encrypt that one file for making an IP block. With ove...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I've used Altera's AMPcrypt tool for that. you only have to encrypt your top level entity, and then create the .qxp file.

you'll need to contact Altera directly to get that tool.

By the way I think I've heard that the new Verilog \ VHDL versions include a built in encryption attribute, but I haven't tried it myself, and I don't know how much Quartus support there is.