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Altera_Forum's avatar
Altera_Forum
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14 years ago

Flattening Verilog Hierarchy for IP block creation

Guys, Wonder if someone could point me in the right direction. I would like to flatten my design hierarchy into 1 file so I can just encrypt that one file for making an IP block. With ove...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

So I tried what 'The brick said'. Looks like you can encrypt your source files and then export the encrypted file as a .qxp and then use the .qxp as normal.

Not tried it in silicon yet but I'll give it a go.

C