Fitter Pin Placement Constraint

The pin assignments should have been back annotated so that they would be written to the .qsf file. If that was not done, you can create manual assignments in the Pin Planner to match what you have set up on the board. Those will get written to the .qsf so they don't change during future compiles.

As for the tools, you can use the Lite edition for free for Max 10 devices. Any recent version will work.

Sorry, but I think there might be a misunderstanding....

The pins were pre-assigned with the pin locations when the Quartus v15.1 tools. Those are in the .qsf file already. Everything compiled OK and the pin locations were used and re-used in various courses where the logic inside the FPGA was changed but the pin locations were always maintained in the same locations.

Moving on to later versions of Quartus but still using the .qsf info from before, the designs created previously with the v15.1 tools, the designs no longer compile because of a Fitter error report. The same pin locations are used and the same FPGA logic is used. But the failure to compile arises when the Fitter (with the later version of Quartus) stops the compile because of the placement of one pin assignment (LED[1]).

So, since I have a board design that was proven with v15.1 tools and that the newer version tools complain with a Fitter error during a design compile, is there a setting that can force the Fitter to ignore the pin assignment error and still complete a design compile?

Charles

That's very strange. What's the exact error you are getting?

There's a patch to fix this in 16.1 at least:

https://www.intel.com/content/www/us/en/support/programmable/articles/000074027.html

This article says it was fixed in 17.0, so not sure why you're seeing it:

https://www.intel.com/content/www/us/en/support/programmable/articles/000087348.html

Have you tried any newer versions of Quartus?

16.1 is no longer available for download. The second link implies that this was a bug that was fixed in 17.0. So the fact that you are seeing it in a newer version is disturbing.

Hi,

There is a restriction rule implemented into quartus from ver 16.0 and above for MAX10 E144 package device. Customer need to avoid output(GPIO) port placed beside PLL inclk.

Try to delete the placement location and instead use the Quartus Auto-Fit placement location. Or manually assign the location of the affected pin away from a PLL clock input pin in Assignment Editor.

https://www.intel.com/content/www/us/en/support/programmable/articles/000087348.html This KDB indicates that previously the Error (18496) can be seen even with Quartus Auto-Fit placement location but had been resolved since ver 17.0

Thanks,

Best Regards,

Sheng

That's great, but any programming files you create will not work with this setup. leds[1] is now connected to somewhere else on the board, hopefully not something that interferes on your board (like power or ground), so any programming files are useless, unless you rework the boards (connect the LED to the new location) to accommodate the change.

sorry but the fix works.

Since there is only ONE GPIO pin available after the .tcl file is changed (all pins are assigned except ONE pin), the Fitter does the Auto-placement of that unassigned output to that pin. The compile does complete and the programming file (.sof) downloads and is fully functional.

I am sorry if I misunderstand your comment, but for other designs in general, where there could be more pins available on the FPGA to use for that output, can't those other pins be marked as "Reserved Pins" so that the Fitter can't use them for auto-placement?

Here is the portion of the Fitter report for the design after employing the work-around change with the .tcl file:

As I mentioned, the compile completes after the auto-placement and the download to the FPGA on our board works as intended.

Thank you everyone for your discussions on this matter.

Charles