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CKPope's avatar
CKPope
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Fitter Pin Placement Constraint

Hello, I am a Lab Instructor at the University of Waterloo. I have to provide some background context for the situation we now have. An in-house board was developed way back when Quartus was still...
Hdl
  • CKPope's avatar
    CKPope
    3 years ago

    Thank you !

    Your work-around solution worked !!!!

    All of the FPGA pins are assigned for the development board that we use in-house.

    We use a .tcl script for the students to run before they begin their FPGA designs. The .tcl script has all pin assignment made.

    When doing a Full Compile (v18.1 LITE) with the assignments the compile fails because of the earlier mentioned Fitter analysis.

    If I then, comment out the pin assignment (see for leds[1] below) and save and run the .tcl file, the FPGA will now have that output pin unassigned.

    Then, like you mentioned, the Fitter will auto-place that output pin to the only available pin left to the FPGA.

    BUT this time, the compile will now complete without any error.

    Thank you so much.

    Charles

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

That's great, but any programming files you create will not work with this setup. leds[1] is now connected to somewhere else on the board, hopefully not something that interferes on your board (like power or ground), so any programming files are useless, unless you rework the boards (connect the LED to the new location) to accommodate the change.