Forum Discussion
New ContributorFitter Pin Placement Constraint
Thank you !
Your work-around solution worked !!!!
All of the FPGA pins are assigned for the development board that we use in-house.
We use a .tcl script for the students to run before they begin their FPGA designs. The .tcl script has all pin assignment made.
When doing a Full Compile (v18.1 LITE) with the assignments the compile fails because of the earlier mentioned Fitter analysis.
If I then, comment out the pin assignment (see for leds[1] below) and save and run the .tcl file, the FPGA will now have that output pin unassigned.
Then, like you mentioned, the Fitter will auto-place that output pin to the only available pin left to the FPGA.
BUT this time, the compile will now complete without any error.
Thank you so much.
Charles
Super ContributorThat's very strange. What's the exact error you are getting?
New ContributorHi SSTRELL
The above compilation result was from using the v18.1 Lite tools.
The same error occurs when using the v18.1 Pin Planner.
When the same design above was compiled with the v15.1 tools, no such Fitter error occurred.
Any ideas are most appreciated.
Charles.
