Forum Discussion

CKPope's avatar
CKPope
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Fitter Pin Placement Constraint

Hello, I am a Lab Instructor at the University of Waterloo. I have to provide some background context for the situation we now have. An in-house board was developed way back when Quartus was still...
Hdl
  • CKPope's avatar
    CKPope
    3 years ago

    Thank you !

    Your work-around solution worked !!!!

    All of the FPGA pins are assigned for the development board that we use in-house.

    We use a .tcl script for the students to run before they begin their FPGA designs. The .tcl script has all pin assignment made.

    When doing a Full Compile (v18.1 LITE) with the assignments the compile fails because of the earlier mentioned Fitter analysis.

    If I then, comment out the pin assignment (see for leds[1] below) and save and run the .tcl file, the FPGA will now have that output pin unassigned.

    Then, like you mentioned, the Fitter will auto-place that output pin to the only available pin left to the FPGA.

    BUT this time, the compile will now complete without any error.

    Thank you so much.

    Charles

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


There is a restriction rule implemented into quartus from ver 16.0 and above for MAX10 E144 package device. Customer need to avoid output(GPIO) port placed beside PLL inclk.


Try to delete the placement location and instead use the Quartus Auto-Fit placement location. Or manually assign the location of the affected pin away from a PLL clock input pin in Assignment Editor.


https://www.intel.com/content/www/us/en/support/programmable/articles/000087348.html This KDB indicates that previously the Error (18496) can be seen even with Quartus Auto-Fit placement location but had been resolved since ver 17.0


Thanks,

Best Regards,

Sheng