Forum Discussion
New ContributorFitter Pin Placement Constraint
Thank you !
Your work-around solution worked !!!!
All of the FPGA pins are assigned for the development board that we use in-house.
We use a .tcl script for the students to run before they begin their FPGA designs. The .tcl script has all pin assignment made.
When doing a Full Compile (v18.1 LITE) with the assignments the compile fails because of the earlier mentioned Fitter analysis.
If I then, comment out the pin assignment (see for leds[1] below) and save and run the .tcl file, the FPGA will now have that output pin unassigned.
Then, like you mentioned, the Fitter will auto-place that output pin to the only available pin left to the FPGA.
BUT this time, the compile will now complete without any error.
Thank you so much.
Charles
New ContributorSorry, but I think there might be a misunderstanding....
The pins were pre-assigned with the pin locations when the Quartus v15.1 tools. Those are in the .qsf file already. Everything compiled OK and the pin locations were used and re-used in various courses where the logic inside the FPGA was changed but the pin locations were always maintained in the same locations.
Moving on to later versions of Quartus but still using the .qsf info from before, the designs created previously with the v15.1 tools, the designs no longer compile because of a Fitter error report. The same pin locations are used and the same FPGA logic is used. But the failure to compile arises when the Fitter (with the later version of Quartus) stops the compile because of the placement of one pin assignment (LED[1]).
So, since I have a board design that was proven with v15.1 tools and that the newer version tools complain with a Fitter error during a design compile, is there a setting that can force the Fitter to ignore the pin assignment error and still complete a design compile?
Charles
