Forum Discussion

CKPope's avatar
CKPope
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Fitter Pin Placement Constraint

Hello, I am a Lab Instructor at the University of Waterloo. I have to provide some background context for the situation we now have. An in-house board was developed way back when Quartus was still...
Hdl
  • CKPope's avatar
    CKPope
    3 years ago

    Thank you !

    Your work-around solution worked !!!!

    All of the FPGA pins are assigned for the development board that we use in-house.

    We use a .tcl script for the students to run before they begin their FPGA designs. The .tcl script has all pin assignment made.

    When doing a Full Compile (v18.1 LITE) with the assignments the compile fails because of the earlier mentioned Fitter analysis.

    If I then, comment out the pin assignment (see for leds[1] below) and save and run the .tcl file, the FPGA will now have that output pin unassigned.

    Then, like you mentioned, the Fitter will auto-place that output pin to the only available pin left to the FPGA.

    BUT this time, the compile will now complete without any error.

    Thank you so much.

    Charles

  • CKPope's avatar
    CKPope
    Icon for New Contributor rankNew Contributor
    3 years ago

    Thank you for that info.

    You sent two links. The first one looks like it is more "in line" with the situation that I am raising.

    The second seems to apply more to the case where pins can be reassigned for an FPGA project.

    Thank you VERY MUCH for this info. I checked the READ_ME file contents for the first link and it mentions that a patch for v16.1 is required. I don't have the v16.1 tools on site but I have the v18.1 tools.

    But I did try creating the quartus.ini file with the "disable....." instruction inside it, with the hope that it would work for the version of Quartus (v18.1)....... but NOPE .

    The patch is definitely required for v16.1 tools.

    But I can't find the v16.1 tools or any patch for later tool versions on the Intel FPGA s/w download site..

    I don't know if you are able to provide any additional info to me or if I could could add something to a TCL file, but anything would be very appreciated.

    Charles