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CKPope's avatar
CKPope
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3 years ago
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Fitter Pin Placement Constraint

Hello, I am a Lab Instructor at the University of Waterloo. I have to provide some background context for the situation we now have. An in-house board was developed way back when Quartus was still...
Hdl
  • CKPope's avatar
    CKPope
    3 years ago

    Thank you !

    Your work-around solution worked !!!!

    All of the FPGA pins are assigned for the development board that we use in-house.

    We use a .tcl script for the students to run before they begin their FPGA designs. The .tcl script has all pin assignment made.

    When doing a Full Compile (v18.1 LITE) with the assignments the compile fails because of the earlier mentioned Fitter analysis.

    If I then, comment out the pin assignment (see for leds[1] below) and save and run the .tcl file, the FPGA will now have that output pin unassigned.

    Then, like you mentioned, the Fitter will auto-place that output pin to the only available pin left to the FPGA.

    BUT this time, the compile will now complete without any error.

    Thank you so much.

    Charles

CKPope's avatar
CKPope
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3 years ago

sorry but the fix works.

Since there is only ONE GPIO pin available after the .tcl file is changed (all pins are assigned except ONE pin), the Fitter does the Auto-placement of that unassigned output to that pin. The compile does complete and the programming file (.sof) downloads and is fully functional.

I am sorry if I misunderstand your comment, but for other designs in general, where there could be more pins available on the FPGA to use for that output, can't those other pins be marked as "Reserved Pins" so that the Fitter can't use them for auto-placement?