Forum Discussion

CKPope's avatar
CKPope
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Fitter Pin Placement Constraint

Hello, I am a Lab Instructor at the University of Waterloo. I have to provide some background context for the situation we now have. An in-house board was developed way back when Quartus was still...
Hdl
  • CKPope's avatar
    CKPope
    3 years ago

    Thank you !

    Your work-around solution worked !!!!

    All of the FPGA pins are assigned for the development board that we use in-house.

    We use a .tcl script for the students to run before they begin their FPGA designs. The .tcl script has all pin assignment made.

    When doing a Full Compile (v18.1 LITE) with the assignments the compile fails because of the earlier mentioned Fitter analysis.

    If I then, comment out the pin assignment (see for leds[1] below) and save and run the .tcl file, the FPGA will now have that output pin unassigned.

    Then, like you mentioned, the Fitter will auto-place that output pin to the only available pin left to the FPGA.

    BUT this time, the compile will now complete without any error.

    Thank you so much.

    Charles

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

The pin assignments should have been back annotated so that they would be written to the .qsf file. If that was not done, you can create manual assignments in the Pin Planner to match what you have set up on the board. Those will get written to the .qsf so they don't change during future compiles.

As for the tools, you can use the Lite edition for free for Max 10 devices. Any recent version will work.