Altera_Forum
Honored Contributor
Honored ContributorFirst verilog project
This is my first work on any FPGA. I have a piece of verilog code I'd like input on. This is a rough start on a module to track an RF signal based on carrier removal and gold code removal. It is assuming input from 2 PLL which it will have to provide feedback to the control logic of.
//correlation module time domain
//------------------------------------------------------
module Correlator_Time_Domain (sampleClock, clk, DIFin, genCodeIn, sinLUT, cosLUT, DLLout, PLLout, DATAout);
parameter SRsize = 32;
input sampleClock;
input clk;
input DIFin;
input genCodeIn;
input sinLUT;
input cosLUT;
output real DLLout;
output real PLLout;
output DATAout;
reg srIl;
reg srIe;
reg srIp;
reg srQl;
reg srQe;
reg srQp;
reg newData;
reg Real, Imag;
reg Ecode, Pcode, Lcode;
reg Ereal, Preal, Lreal, Eimag, Pimag, Limag;
integer sumIe, sumIp, sumIl, sumQe, sumQp, sumQl, p;
always @ (posedge sampleClock) //4.096Mhz sampleClock with NCO //may change this
begin
Real = DIFin ^ sinLUT;
Imag = DIFin ^ cosLUT;
Ereal = Real ^ Ecode;
Preal = Real ^ Pcode;
Lreal = Real ^ Lcode;
Eimag = Imag ^ Ecode;
Pimag = Imag ^ Pcode;
Limag = Imag ^ Lcode;
newData = 1;
end
always @ (posedge clk) //50Mhz main reference
begin
if( newData == 1)
begin
//shift new samples into shift register for summation
srIl = srIl;
srIl = Lreal;
srIe = srIe;
srIe = Ereal;
srIp = srIp;
srIp = Preal;
srQl = srQl;
srQl = Limag;
srQe = srQe;
srQe = Eimag;
srQp = srQp;
srQp = Pimag;
//sum shift register values
for(p = 1; p < SRsize; p = p+1)
begin
sumIe = srIe + srIe;
sumIp = srIp + srIp;
sumIl = srIl + srIl;
sumQe = srQe + srQe;
sumQp = srQp + srQp;
sumQl = srQl + srQl;
end
//compute outputs
assign DLLout = ((sumIe*sumIe + sumQe*sumQe)-(sumIl*sumIl + sumQl*sumQl)) / 2; //early - late error value
assign PLLout = atan(sumQp / sumIp); //0-90 degree phase error
//sum nav data //need to add still
newData = 0;
end
end
endmodule
