First verilog project

So as long as I split them up and do the blocking assignment int intermediate variable seperate it should function.

always @ (posedge sysclk)
	begin
		//do averaging
		IEint = 32'h00000000;
		IPint = 32'h00000000;
		ILint = 32'h00000000;
		QEint = 32'h00000000;
		QPint = 32'h00000000;
		QLint = 32'h00000000;
		for(n=0; n<N; n= n+1)
		begin
			IEint = IEint + Iearly;
			IPint = IPint + Iprompt;
			ILint = ILint + Ilate;
			QEint = QEint + Qearly;
			QPint = QPint + Qprompt;
			QLint = QLint + Qlate;
		end
	end
	always @ (posedge sysclk)
	begin
		IEtotal <= IEint / N;
		IPtotal <= IPint / N;
		ILtotal <= ILint / N;
		QEtotal <= QEint / N;
		QPtotal <= QPint / N;
		QLtotal <= QLint / N;
		//calculate control
		

My next question would be on an NCO. This is based on a simple sawtooth example I found for fixed freq output. If I feed the output to a sin and cos LUT I should be able to get my mixer values to quadrature split and remove carrier drift from the PRN. Does this code look correct?

module NCOcarrier(sampleclk, NCOout, control);
	input sampleclk;
	input  control;     //how to apply control? + or - to IF
	output  NCOout;				 //control 00 stay, 01 increase, 11 decrease chip rate
	reg  signalOut = 32'd0;
	integer IF = 12000000;    //set to center IF
	
	
	always @ (posedge sampleclk)
	begin
		if(control == 2'b01)
		begin
			rate = rate + 1; //how much to advance or retard
		end
		if(control == 2'b11)
		begin
			rate = rate - 1;
		end
	end
		
	always @ (posedge sampleclk)
	begin
		signalOut <= signalOut + IF * 64'h100000000 / 50000000;
	end
	assign NCOout = signalOut;  //use signalOut as input value for LUT sin and cos
endmodule

How would I handle roll over of the 32 bit signalOut value? Seems like the value should be kept within 0-90degrees or equivelent to, so as to keep the LUT as small as possible. I'm going to have to think on that one a while.