First verilog project

I believe you haven't compiled the code. Quartus will report most errors, especially syntax related.

Some fatal syntax errors are,

- "assign" cannot be placed in procedural blocks, such as within the "always"

- "real" outputs cannot be synthesized

- atan is likely unsupported

Non-fatal but violate RTL rules,

- Procedural block with edged sensitivity list "always @(posedge...)" should use non-blocking assignments, ie <= instead of =

Non-syntactical but likely not what you want

- The loop of sumIe...sumQ1 has only the last p index useful. All those p=1 to SRsize-2 are overwritten

- Integer data type should not be used as nodes. How wide the bus you need for, say sumIe?

- Direct use of multiplier (*) may not fit well in FPGA without multipliers. It will be large and slow

Logical errors,

- The 2 clks are not phase related, the use of "newdata" in 2nd "always" needs proper synchronization.

- Both clks update "newdata", what do you want it to synthesize? A flip-flop with 2 clks?