First verilog project

I appreciate your responses

I'm trying to keep it on a logic circuit flow. I'v split some of the functions down into seperate modules. Hopefully I can keep it better organized. It is fully compiling as it is with only a few errors. Pins incomplete IO assignments, I have not run through the pin placement yet. No clocks in design, i still have to figure out how to go about setting those up. Verilog HDL assignment warning at Basestation1.v(75): truncated value with size 4096 to match size of target (4095). I am not certain where I've got it wrong with that one. Those warnings apply to all of my shift registers.

module Correlator_Time_Domain_CA (sampleClock, DIFin, sinLUT, cosLUT, chipIN, IEout, IPout, ILout, QEout, QPout, QLout);
	input sampleClock;        //4.096Mhz
	input DIFin, sinLUT, cosLUT;
	input chipIN;
	
	output IEout, IPout, ILout, QEout, QPout, QLout;
	
	reg chip;
	reg result;
	
	always @ (posedge sampleClock)
	begin
		chip <= {chip, chipIN};        //shift in new early chip to lsb
		result <= DIFin ^ sinLUT ^ chip;
		result <= DIFin ^ sinLUT ^ chip;
		result <= DIFin ^ sinLUT ^ chip;
		result <= DIFin ^ cosLUT ^ chip;
		result <= DIFin ^ cosLUT ^ chip;
		result <= DIFin ^ cosLUT ^ chip;
		
			
	end
	assign ILout = result;
	assign IPout = result;
	assign IEout = result;
	assign QLout = result;
	assign QPout = result;
	assign QEout = result;
endmodule

Then this is the next step, an adder module

module code_ADDER#  (parameter N = 4096)(IL, IP, IE, QE, QP, QL, sysclk, codeNCOctl, phaseNCOctl);
	input sysclk;          //50Mhz
	input IL, IP, IE, QL, QP, QE;
	output codeNCOctl;
	output phaseNCOctl;	
	integer n;
	reg Iearly;
	reg Iprompt;
	reg Ilate;
	reg Qearly;
	reg Qprompt;
	reg Qlate;
	reg  IEtotal, IPtotal, ILtotal, QEtotal, QPtotal, QLtotal;
	reg codeAdvance;
	reg phaseAdvance;
	
	always @ (posedge sysclk)
	begin
		Iearly  <= {Iearly, IE};
		Iprompt <= {Iprompt, IP};
		Ilate   <= {Ilate, IL};
		Qearly  <= {Qearly, QE};
		Qprompt <= {Qprompt, QP};
		Qlate   <= {Qlate, QL};
		//do averaging
		IEtotal <= 32'b00000000000000000000000000000000;
		IPtotal <= 32'b00000000000000000000000000000000;
		ILtotal <= 32'b00000000000000000000000000000000;
		QEtotal <= 32'b00000000000000000000000000000000;
		QPtotal <= 32'b00000000000000000000000000000000;
		QLtotal <= 32'b00000000000000000000000000000000;
		for(n=0; n<4096; n= n+1)
		begin
			IEtotal <= IEtotal + Iearly;
			IPtotal <= IPtotal  + Iprompt;
			ILtotal <= ILtotal + Ilate;
			QEtotal <= QEtotal + Qearly;
			QPtotal <= QPtotal + Qprompt;
			QLtotal <= QLtotal + Qlate;
		end
		
		IPtotal <= IPtotal / N;
		
		QEtotal <= QEtotal / N;
		QPtotal <= QPtotal / N;
		QLtotal <= QLtotal / N;
		//calculate control
		if(IEtotal/N > ILtotal/N)
		begin
			codeAdvance <= 2'b11;
		end
		else if(IEtotal/N < ILtotal/N)
		begin
			codeAdvance <= 2'b01;
		end
		else 
		begin
			codeAdvance <= 2'b00;
		end	
		if(QEtotal * QLtotal > 1)
		begin
			phaseAdvance <= 2'b11;  //control bits to advance or retard NCO module
		end
		else if (QEtotal < 1)
		begin
			phaseAdvance <= 2'b01;
		end
		else
		begin
			phaseAdvance <= 2'b00;
		end
	end
	assign codeNCOctl = codeAdvance;
	assign phaseNCOctl = phaseAdvance;
	
endmodule

I'm wondering about the adder function. Is there a good model to follow in syncronizing one module to the next when one does accumulate and averaging operations?