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Altera_Forum
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11 years ago

First verilog project

This is my first work on any FPGA. I have a piece of verilog code I'd like input on. This is a rough start on a module to track an RF signal based on carrier removal and gold code removal. It is assu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

So from what I've read so long as the "IEtotal_intermediate" variable is only used inside of the "always" block then use of the blocking "=" operator will work as an accumulator(would you call it a deterministic local variable?) , but if it was also used outside of that always block it would be used as a flip flop as if it had been a non blocking "<=" operator to start with?(non-deterministic?)

Is it important to also make the distiction you did in the example of + {31 bits , 1 bit input}? Is it just a better notation or will lack of being specific and just adding + 1 bit input cause a problem?

Thanks again