First verilog project

I see the logic error in the for loops changed to

//sum shift register values
			sumIe = srIe;
			sumIp = srIp;
			sumIl = srIl;
			sumQe = srQe;
			sumQp = srQp;
			sumQl = srQl; 
			for(p = 1; p < SRsize; p = p+1)
				begin
				sumIe = sumIe + srIe;
				sumIp = sumIp + srIp;
				sumIl = sumIl + srIl;
				sumQe = sumQe + srQe;
				sumQp = sumQp + srQp;
				sumQl = sumQl + srQl;
				end

When I try a compile in Quartus2 vers 13.1 I get this current build errors

--- Quote Start ---

Info (12021): Found 3 design units, including 3 entities, in source file basestation1.v

Info (12023): Found entity 1: search

Info (12023): Found entity 2: Correlator_Time_Domain

Info (12023): Found entity 3: NCO

Info (12021): Found 1 design units, including 1 entities, in source file basestation.bdf

Info (12023): Found entity 1: Basestation

Info (12021): Found 1 design units, including 1 entities, in source file codegenerator.v

Info (12023): Found entity 1: CACODE

Warning (10236): Verilog HDL Implicit Net warning at Basestation1.v(118): created implicit net for "sine_lookup_output"

Error (12007): Top-level design entity "Basestation1" is undefined

Info (144001): Generated suppressed messages file C:/Altera/projects/output_files/Basestation1.map.smsg

Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 1 error, 2 warnings

Error: Peak virtual memory: 345 megabytes

Error: Processing ended: Sun Apr 20 22:23:13 2014

Error: Elapsed time: 00:00:02

Error: Total CPU time (on all processors): 00:00:01

Error (293001): Quartus II Full Compilation was unsuccessful. 3 errors, 2 warnings

--- Quote End ---

Can I not run 2 operations in the same module? I know the calculation part will take more reference clock cycles than the signal input so I was trying to use "newData" essentially as a boolean value with the always block running at the reference clock checking to see "IF" it was set to 1 by the input block. Can I not work it that way?

I'm completely new to FPGA design.