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Altera_Forum
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11 years ago

First verilog project

This is my first work on any FPGA. I have a piece of verilog code I'd like input on. This is a rough start on a module to track an RF signal based on carrier removal and gold code removal. It is assu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Blocking(=) and non-blocking(<=) assignments are different in Verilog.

Non-blocking assignments have RHS evaluated immediately, but the results are updated at the end of time step. When there are multiple assignments to the same node in the same time step, the last one overrides. The IEtotal depends on uninitialized IEtotal, that makes it undeterministic.

Blocking assignments are evaluated sequentially. LHS is updated immediately before moving on to evaluate the next statement. Accumulator loop will work.

In RTL, we do not mix blocking and non-blocking in the same "always" block. This rule is set to ensure consistent behavior comparing simulator with synthesized logic. You can actually change the <= to = in the old code and notice correct simulation behavior, but it will not work on hardware. Most likely a warning is generated during synthesis.

About the {31'h0000000, Iearly[n]}, it is a good practise to keep both sides of an equation having the same bus width. Also to get rid of annoying warnings.