Honored Contributor
Honored ContributorFPGA is not the problem. I think the biggest skill you lack is RTL coding.
Get a book about Verilog that discusses RTL. It should not be difficult to pick up assumming you have digital logic design background. We can go with specific problem here. Without foundation in HDL, I see that it will take a long while to talk through all problems. In the mean time, about what you posted, - HDL is not software programming. We don't normally code cummulative sumIe in RTL using loop because not all synthesis tools accept this. Not sure about Quartus - The Quartus error was about missing Basestation1, which was indicated as top-level design. I guess basestation.bdf is your top-level file. If so, use basestation as top-level design name - As of newData, think about what you want the circuit to be, then translate it to code. Remember, HDL does not behave like software. Metastability has be considered transferring signal across asynchrounous clock domains
