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Altera_Forum
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11 years ago

First verilog project

This is my first work on any FPGA. I have a piece of verilog code I'd like input on. This is a rough start on a module to track an RF signal based on carrier removal and gold code removal. It is assu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Of the first piece of code, its sensitivity list should not be edge triggered to model combinatorial logic. Make it "always @*".

As of the NCO,

- Both rate and signalOut are uninitialized. Keep in mind that registers are unknowns upon circuit power-up. All branches in the assignments have dependency on old content. Therefore, both registers cannot get meaningful value. You need to find a way to reset or load the registers

- rate should use <= in assignment

- The module has only one output, NCOout. Not sure why the rate and control need to be there. They cannot affect NCOout in any way.

About the truncation of NCOout, it depends how many LUT entries you can afford, effectively the trigo's resolution. You can't be having 2^32 entries. Why not reduce the width of signalOut?