FIFO Outputs all HiZ in RTL Simulation

From the attached waveform, it seems you have tied the FIFO reset signal to one. I think its reset signal is active-high; If so, drive it with '1', and after a few clock cycles drive it with '0'.

What did you put in the testbench? It looks like there is nothing more than a clock and a reset stuck at 1

Right now the test bench IS just a clock signal. I added in a reset to 1 in that screenshot just to try it out. Whether it is 1 or 0, the outputs are still HiZ. I also tried what msj suggested, which was drive reset to 1 for a few clocks, then drive to 0. Still no change.

have you actually connected the clock to the FIFO? how about the other signals?

what is clock frequency? Are you simulating a post-place & route design or a pre-synthesis one?

I'll be totally honest with you, I was running commands directly in ModelSim just to experiement. That is probably a dumb thing to do. I wrote a test bench which produces the attached output.

`timescale 1ns / 100ps
module sync_fifo_tb ();
  
  //
  // Inputs to module
  reg clk;
  reg wrreq;
  reg rdreq;
  reg data;
  reg sclr;
  
  //
  // Outputs from module
  wire q;
  wire usedw;
  wire full;
  wire empty;
  
  //
  // Instantiate device
  sync_fifo U1(
        .clock(clk),
        .data(data),
        .rdreq(rdreq),
        .sclr(sclr),
        .wrreq(wrreq),
        .empty(empty),
        .full(full),
        .q(q),
        .usedw(usedw)
        );
        
  //
  // Clock setup
  always
   # 5 clk = ~clk;
  
  //
  // Initial setup
  initial
  begin
    clk = 0;
    sclr = 1;
    wrreq = 0;
    rdreq = 0;
    data = 8'b10101010;
    
   # 50 sclr = 0;
    
   # 20 wrreq = 1;
    @(posedge clk); // Wait 5 clocks
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
   # 5 wrreq = 0;
  end
  
endmodule

I posted a test bench file, but that is awaiting moderation for some reason. In the meantime, I'm not entirely sure how to answer that question msj.

meanwhile, run simulator without optimization:

"vsim -novopt work.sync_fifo_tb -L altera_mf" produces no change. I even recompiled with -O0 first.