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Altera_Forum
Honored Contributor
Honored ContributorFIFO Outputs all HiZ in RTL Simulation
Hi All, I am still a beginner to FPGAs, but I think I'm making good progress. I am able to simulate my own Verilog code in ModelSim-Altera and everything looks correct. However, when I tr...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I'll be totally honest with you, I was running commands directly in ModelSim just to experiement. That is probably a dumb thing to do. I wrote a test bench which produces the attached output. --- Quote End --- Ive unblocked all your posts - posting code with low post numbers requires moderation. No, that is a perfectly normal thing to do (and much better than running it from quartus). Have you compiled the sync_fifo block? where is the code for that?
