FIFO Outputs all HiZ in RTL Simulation

I'll be totally honest with you, I was running commands directly in ModelSim just to experiement. That is probably a dumb thing to do. I wrote a test bench which produces the attached output.

`timescale 1ns / 100ps
module sync_fifo_tb ();
  
  //
  // Inputs to module
  reg clk;
  reg wrreq;
  reg rdreq;
  reg data;
  reg sclr;
  
  //
  // Outputs from module
  wire q;
  wire usedw;
  wire full;
  wire empty;
  
  //
  // Instantiate device
  sync_fifo U1(
        .clock(clk),
        .data(data),
        .rdreq(rdreq),
        .sclr(sclr),
        .wrreq(wrreq),
        .empty(empty),
        .full(full),
        .q(q),
        .usedw(usedw)
        );
        
  //
  // Clock setup
  always
   # 5 clk = ~clk;
  
  //
  // Initial setup
  initial
  begin
    clk = 0;
    sclr = 1;
    wrreq = 0;
    rdreq = 0;
    data = 8'b10101010;
    
   # 50 sclr = 0;
    
   # 20 wrreq = 1;
    @(posedge clk); // Wait 5 clocks
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
   # 5 wrreq = 0;
  end
  
endmodule